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m68hc05 microcontrollers freescale.com mc68hc05sr3 mc68hc705sr3 technical data mc68hc05sr3d/h rev. 2.1 08/2005

1 2 3 4 5 6 7 8 9 10 11 12 a general description pin descriptions input/output ports memory and registers resets and interrupts timer analog to digital converter cpu core and in struction set low power modes operating modes electrical specifications mechanical specifications mc68hc705sr3 tpg 1 05sr3.book page 3 thursday, august 4, 2005 1:08 pm
1 2 3 4 5 6 7 8 9 10 11 12 a general description pin descriptions input/output ports memory and registers resets and interrupts timer analog to digi tal converter cpu core and instruction set low power modes operating modes electrical specifications mechanical specifications mc68hc705sr3 tpg 2 05sr3.book page 4 thursday, august 4, 2005 1:08 pm
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tpg 4 conventions register and bit mnemonics are defined in the paragraphs describing them. an overbar is used to designate an active-low signal, eg: reset . unless otherwise stated, blank cells in a register diagram indicate that the bit is either unused or reserved; shaded cells indicate that the bit is not described in the following paragraphs; ?u? is used to indicate an undefined state (on reset). 05sr3.book page 6 thursday, august 4, 2005 1:08 pm
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mc68hc05sr3 freescale i paragraph number page number title table of contents 1 general description 1.1 features.................................................................................................................1-1 1.2 mask options.........................................................................................................1-2 2 pin descriptions 2.1 functional pin descriptions ... .............. .............. .............. .............. .............. ..........2-1 2.2 osc1 and osc2 connections .... .............. .............. .............. .............. ........... .......2-2 2.2.1 crystal oscillator..............................................................................................2-3 2.2.2 external clock..................................................................................................2-3 2.2.3 rc oscillator option ........................................................................................2-4 2.3 pin assignments ....................................................................................................2-5 3 input/output ports 3.1 parallel ports .........................................................................................................3-1 3.1.1 port data registers..........................................................................................3-1 3.1.2 port data direction registers ..........................................................................3-2 3.2 port a ? keyboard interrupts (kbi) ............. .............. .............. ........... ........... .......3-2 3.3 pd0:pd5 ? adc inputs........ .............. .............. .............. .............. .............. ..........3-2 3.4 pd6 ? irq2 ..........................................................................................................3-3 3.5 programmable current drive .................................................................................3-3 3.6 programmable pull-up devices.............................................................................3-5 3.6.1 port option register ........................................................................................3-5 tpg 7 05sr3.book page i thursday, august 4, 2005 1:08 pm
freescale ii mc68hc05sr3 paragraph number page number title 4 memory and registers 4.1 i/o registers ......................................................................................................... 4-1 4.2 ram ......................................................................................................................4-1 4.3 rom ......................................................................................................................4-1 4.4 memory map ......................................................................................................... 4-2 4.5 i/o registers summary .........................................................................................4-3 5 resets and interrupts 5.1 resets ........... .............. .............. .............. .............. .............. .............. ........... ......5-1 5.1.1 power-on reset (por) ................................................................................... 5-1 5.1.2 reset pin.......................................................................................................5-1 5.1.3 low voltage reset (lvr) ... .............. .............. .............. .............. .............. ........5-2 5.2 interrupts........................................................................................................5-2 5.2.1 non-maskable software interrupt (swi) .. ........................................................5-3 5.2.2 maskable hardware interrupts.........................................................................5-5 5.2.2.1 external interrupt (irq )..............................................................................5-5 5.2.2.2 external interrupt 2 (irq2 ).........................................................................5-7 5.2.2.3 timer interrupt ........................................................................................... 5-7 5.2.2.4 keyboard interrupt (kbi) ............................................................................5-8 6 timer 6.1 timer overview .....................................................................................................6-1 6.2 timer control register (tcr) ............................................................................... 6-3 6.3 timer data register (tdr) ................................................................................... 6-4 6.4 operation during low power modes ..................................................................... 6-4 7 analog to digital converter 7.1 adc operation ...................................................................................................... 7-2 7.2 adc status and control register (adscr)..........................................................7-3 7.3 adc data register (addr) .................................................................................. 7-4 7.4 adc during low power modes..............................................................................7-4 tpg 8 05sr3.book page ii thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale iii paragraph number page number title 8 cpu core and instruction set 8.1 registers ...............................................................................................................8-1 8.1.1 accumulator (a) ...............................................................................................8-1 8.1.2 index register (x)..............................................................................................8-2 8.1.3 program counter (pc) ......................................................................................8-2 8.1.4 stack pointer (sp) ............................................................................................8-2 8.1.5 condition code register (ccr).......... .............. .............. .............. .............. .......8-2 8.2 instruction set ........................................................................................................8-3 8.2.1 register/memory instructions ..........................................................................8-4 8.2.2 branch instructions ..........................................................................................8-4 8.2.3 bit manipulation instructions ............................................................................8-4 8.2.4 read/modify/write instructions .........................................................................8-4 8.2.5 control instructions ..........................................................................................8-4 8.2.6 tables...............................................................................................................8-4 8.3 addressing modes .................................................................................................8-11 8.3.1 inherent............................................................................................................8-11 8.3.2 immediate ........................................................................................................8-11 8.3.3 direct................................................................................................................8-11 8.3.4 extended......... .............. .............. .............. .............. .............. ............ ........... ....8-12 8.3.5 indexed, no offset.............................................................................................8-12 8.3.6 indexed, 8-bit offset.............................. ............................................................8-12 8.3.7 indexed, 16-bit offset........................................................................................8-12 8.3.8 relative ............................................................................................................8-13 8.3.9 bit set/clear ......................................................................................................8-13 8.3.10 bit test and branch ...........................................................................................8-13 9 low power modes 9.1 stop mode ...........................................................................................................9-1 9.2 wait mode............................................................................................................9-1 9.3 slow mode ..........................................................................................................9-3 9.4 data-retention mode ............................................................................................9-3 10 operating modes 10.1 user mode ...........................................................................................................10-1 10.2 self-check mode .................................................................................................10-1 10.3 bootstrap mode ...................................................................................................10-3 tpg 9 05sr3.book page iii thursday, august 4, 2005 1:08 pm
freescale iv mc68hc05sr3 paragraph number page number title 11 electrical specifications 11.1 maximum ratings................................................................................................ 11-1 11.2 thermal characteristics ...................................................................................... 11-1 11.3 dc electrical characteristics............................................................................... 11-2 11.4 adc electrical characteristics ............................................................................ 11-4 11.5 control timing ..................................................................................................... 11-5 12 mechanical specifications 12.1 40-pin dip package (case 711-03) .................................................................... 12-2 12.2 42-pin sdip package (case 858-01) ............ .............. .............. ........... ........... .... 12-2 12.3 44-pin qfp package (case 824a-01) ................................................................. 12-3 a mc68hc705sr3 a.1 features ............................................................................................................... a-1 a.2 modes of operation .............................................................................................. a-2 a.3 user mode ............................................................................................................ a-2 a.4 bootstrap mode .................................................................................................... a-2 a.4.1 eprom programming .................................................................................... a-3 a.4.2 program control register (pcr) .................................................................... a-3 a.4.3 eprom programming sequence ................................................................... a-3 a.5 mask option register (mor) ............................................................................... a-4 a.6 pin assignments................................................................................................... a-5 tpg 10 05sr3.book page iv thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale v figure number page number title list of figures 1-1 mc68hc05sr3/ mc68hc705sr3 block diagram................................................ 1-3 2-1 oscillator connections............................................................................................ 2-3 2-2 typical oscillator frequency for selected external resistor .................................. 2-4 2-3 typical oscillator frequency for wire-str ap connection .............. ........... ............ ... 2-4 2-4 pin assignment for 40-pin pdip ............... .............................................................. 2-5 2-5 pin assignment for 42-pin sdip ............... .............................................................. 2-6 2-6 pin assignment for 44-pin qfp ................ .............................................................. 2-6 3-1 port i/o circuitry ..................................................................................................... 3-2 3-2 typical iol vs vol @vdd=5v.............................................................................. 3-3 3-3 typical ioh vs voh @vdd=5v............................................................................. 3-4 3-4 typical iol vs vol @vdd=3v.............................................................................. 3-4 3-5 typical iol vs vol @vdd=3v.............................................................................. 3-5 4-1 mc68hc05sr3/mc68hc705sr3 memory map ................................................... 4-2 5-1 interrupt stacking order ......................................................................................... 5-3 5-2 hardware interrupt processing flowchart .............................................................. 5-4 5-3 external interrupt.................................................................................................... 5-6 5-4 keyboard interrupt circuitry.................................................................................... 5-8 6-1 timer block diagram .............................................................................................. 6-2 7-1 adc converter block diagram ............................................................................... 7-1 8-1 programming model ................................. .............................................................. 8-1 8-2 stacking order ........................................................................................................ 8-2 9-1 stop and wait mode flowcharts......................................................................... 9-2 10-1 mc68hc05sr3 self-check circuit ............. ......................................................... 10-2 12-1 40-pin dip package.............................................................................................. 12-2 12-2 42-pin sdip package ........................................................................................... 12-2 12-3 44-pin qfp package ............................................................................................ 12-3 tpg 11 05sr3.book page v thursday, august 4, 2005 1:08 pm
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mc68hc05sr3 freescale vii ta bl e number page number title list of tables 1-1 power-on reset delay mask option ...................................................................... 1-2 3-1 i/o pin functions .................................................................................................... 3-1 4-1 mc68hc05sr3/mc68hc705sr3 i/o register s ................................................... 4-3 5-1 reset/interrupt vector addresses .......................................................................... 5-3 7-1 adc channel assignments .................................................................................... 7-4 8-1 mul instruction ...................................................................................................... 8-5 8-2 register/memory instructions................................................................................. 8-5 8-3 branch instructions ................................................................................................. 8-6 8-4 bit manipulation instructions................................................................................... 8-6 8-5 read/modify/write instructions ............................................................................... 8-7 8-6 control instructions................................................................................................. 8-7 8-7 instruction set ......................................................................................................... 8-8 8-8 m68hc05 opcode map........................................................................................... 8-10 10-1 mode selection....... .............. .............. .............. .............. ........... ............ ........... .... 10-1 10-2 self-check report ................................................................................................ 10-3 11-1 dc electrical characteristics for 5v operation..................................................... 11-2 11-2 dc electrical characteristics for 3v operation..................................................... 11-3 11-3 adc electrical characteristics for 5v and 3v operation...................................... 11-4 11-4 control timing for 5v operation ........................................................................... 11-5 11-5 control timing for 3v operation ........................................................................... 11-6 a-1 mc68hc705sr3 operating mode entry c onditions ........... .............. .............. ......a-2 tpg 13 05sr3.book page vii thursday, august 4, 2005 1:08 pm
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mc68hc05sr3 freescale 1-1 general description 1 1 general description the mc68hc05sr3 hcmos microcontroller is a me mber of the m68hc05 family of low-cost single-chip microcontrollers. this 8-bit microcontroller unit (mcu) contains on-chip oscillator, cpu, ram, rom, i/o, timer, and analog-to-digital converter. the mc68hc05sr3 is pin compatible with the mc6805r3 and is provided as a low power upgrade path for mc6805r3 applications. the low power advantage of cmos is combined with the addition of i/o and port modifications which help eliminate external components in cost sensitive applications. the mc68hc705sr3 is an eprom version of th e mc68hc05sr3; it is available in windowed and otp packages. all references to the mc68hc05sr3 apply equally to the mc68hc705sr3, unless otherwise stated. references specific to the mc68hc705 sr3 are italicized in the text and also, for quick reference, they are summarized in appendix a. 1.1 features fully static chip design featuring t he industry standard 8-bit m68hc05 core pin compatible with the mc6805r3 power saving stop, wait, and slow modes 3840 bytes of user rom with security feature in mc68hc05sr3 3840 bytes of eprom with security bit in mc68hc705sr3 192 bytes of ram (64 bytes for stack) 32 bidirectional i/o lines keyboard interrupts 8-bit count-down timer with programmable 7-bit prescaler on-chip crystal oscillator, with built-in capacitor for rc option second software programmable external interrupt line (irq2 ) direct led drive capability on all ports programmable 20k ? pull-up resistors integrated into i/o ports tpg 15 05sr3.book page 1 thursday, august 4, 2005 1:08 pm
freescale 1-2 mc68hc05sr3 general description 1 internal 100k ? pull-up resistors on irq and reset pins four channel 8-bit analog to digital converter low voltage reset available in 40-pin pdip, 42-pin sdip and 44-pin qfp packages 1.2 mask options the following mask options are available: rc or crystal oscillator (see sectio n 2.2). the default is crystal option. power-on reset delay ? table 1-1 shows available options. the default value is 4096 cycles. power-on reset slow mode. if enabled, the device goes into slow mode directly upon power-on reset. the bus frequency is 16 times slower than the normal mode. thus, the power-on reset delay will also be 16 times longer. the default setting is ?slow mode? disabled. table 1-1 power-on reset delay mask option power-on reset delay (cycles) 256 512 1024 2048 4096 8192 16384 32768 tpg 16 05sr3.book page 2 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale 1-3 general description 1 figure 1-1 mc68hc05sr3/ mc68hc705sr3 block diagram user rom/ eprom - 3840 bytes self-check/ bootstrap rom - 240 bytes ram - 192 bytes accumulator index register stack pointer program counter condition code register m68hc05 cpu reset irq 0 12 1 1h i nzc osc power osc1 osc2 vdd vss ddr a port a pa0 - pa7 8 2 1 1 7 0 7 50 1 0 0 0 0 0 0 4 15 0 7 ddr b port b pb0 - pb7 8-bit adc port d 8 ddr c port c pc0 - pc7 8 7-bit prescaler keyboard interrupt pd7 pd6/irq2 pd5/v rh pd4/v rl pd3/an3 pd2/an2 pd1/an1 pd0/an0 8-bit counter timer control timer low voltage reset reset ddr d tpg 17 05sr3.book page 3 thursday, august 4, 2005 1:08 pm
freescale 1-4 mc68hc05sr3 general description 1 this page left bl ank intentionally tpg 18 05sr3.book page 4 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale 2-1 pin descriptions 2 2 pin descriptions this section provides a description of the func tional pins of the mc68hc05sr3 microcontroller. 2.1 functional pin descriptions pin name 40-pin pdip pin no. 42-pin sdip pin no. 44-pin qfp pin no. description vdd vss vss(int) vss(ext) 4 1 ? ? 5 ? 1 2 10, 33 32 6 7 power is supplied to the mcu using these pins. vdd should be connected to the positive supply. vss, vss(int), and vss(ext) should be connected to supply ground. vpp 7 8 13 this is the eprom progra mming voltage input pin on the mc68hc705sr3. on the mc68hc05sr3 part, this pin should be connected to vdd or vss. irq 349 irq is software programmable to provide two choices of interrupt triggering sensitivity. these options are: 1) negative-edge-sensitive triggering only, or 2) both negative-edge-sensitive and level-sensitive triggering. this pin has an integrated pull -up resistor to vdd but should be tied to vdd if not needed to improve noise immunity. the irq pin contains an internal sc hmitt trigger as part of its input to improve noise immunity. the voltage on this pin may affect the mode of operation as described in section 10. reset 238 this pin can be used as an input to reset the mcu to a known start-up state by pulling it to the low state. the reset pin contains an internal schmitt trigger to improve its noise immunity as an inpu t. it also has an internal pull-down device that pulls the reset pin low during the power-on reset cycles and an in tegrated pull-up resistor to vdd. timer 8 9 14 the timer pin provides an optional gating input to the timer. refer to section 6 for additional information. osc1, osc2 5, 6 6, 7 11, 12 the osc1 and osc2 pins are the connections for the on-chip oscillator. see section 2.2 for detail. tpg 19 05sr3.book page 1 thursday, august 4, 2005 1:08 pm
freescale 2-2 mc68hc05sr3 pin descriptions 2 2.2 osc1 and osc2 connections the osc1 and osc2 pins are the connections fo r the on-chip oscillator ? the following configurations are available: 1) a crystal or ceramic resonator as shown in figure 2-1(a). 2) an external clock signal as shown in figure 2-1(b). 3) rc options as shown in figure 2-1(c) and figure 2-1(d). pa0-pa7 33-40 34-41 42-44, 1-5 these eight i/o lines comprise port a. the state of any pin is software programmable. all port a lines are configured as input during power-on or external reset. pa0-pa7 are also associated with the keyboard interrupt function. each pin is equipped with a programmable integrated 20k ? pull-up resistor connected to vdd when configured as input. when pr ogrammed as output, each pin can provide a current drive of 10ma. see section 3 for details on the i/o ports. pb0-pb7 25-32 26-33 31, 35-41 these eight i/o lines comprise port b. the state of any pin is software programmable. all port b lines are configured as input during power-on or external reset. each pin is equipped with a programmable integrated 20k ? pull-up resistor connected to vdd when configured as input. when programmed as output, each pin can provide a current drive of 10ma. pb5-pb7 can also be programmed to provide a lower current drive of 2ma. see section 3 for details on the i/o ports. pc0-pc7 9-16 10-17 15-22 these eight i/o lines comprise port c. the state of any pin is software programmable. all po rt c lines are configured as input during power-on or external reset. each pin is equipped with a programmable integrated 20k ? pull-up resistor connected to vdd when configured as input. when programmed as output, each pin can provide a current drive of 10ma. see section 3 for details on the i/o ports. pd0-pd7 an0-an3 irq2 vrh vrl 24-21, 20-17 24-21 18 19 20 25-22, 21-18 25-22 19 20 21 30-23 30-27 24 25 26 these eight i/o lines comprise port d. the state of any pin is software programmable. all po rt d lines are configured as input during power-on or external reset. each pin is equipped with a programmable integrated 20k ? pull-up resistor connected to vdd when configured as input. when programmed as output, each pin can provide a current drive of 10ma. pd0-pd3 become analog inputs an0-an3 when the adon bit is set in the adc status and control register ($0e). pd4 and pd5 becomes vrl and vrh respectively for the adc reference voltage inputs. pd6 is configured as irq2 by setting irq2e in the miscellaneous control register ($0c). see section 3 for details on the i/o ports. pin name 40-pin pdip pin no. 42-pin sdip pin no. 44-pin qfp pin no. description tpg 20 05sr3.book page 2 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale 2-3 pin descriptions 2 the external oscillator clock frequency, f osc , is divided by two to produce the internal operating frequency, f op . 2.2.1 crystal oscillator the circuit in figure 2-1(a) shows a typical oscillat or circuit for an at-cut, parallel resonant crystal. the crystal manufacturer?s recommendations s hould be followed, as the crystal parameters determine the external component values requ ired to provide maximum stability and reliable start-up. the load capacitance values used in the oscillator circuit design should include all stray capacitances. the crystal and components should be mounted as close as possible to the pins for start-up stabilization and to minimize output distortion. an external start-up resistor of approximately 10m ? is needed between osc1 and osc2 for the crystal type oscillator. 2.2.2 external clock an external clock from another cmos-compatible device can be connected to the osc1 input, with the osc2 input not connected, as shown in figure 2-1(b). figure 2-1 oscillator connections osc1 osc2 25p 25p 10m ? v dd osc1 osc2 external clock unconnected osc1 osc2 osc1 osc2 unconnected r mcu mcu mcu mcu (a) crystal or ceramic resonator connections (b) external clock source connection (c) rc option 1 - external resistor (d) rc option 2 - internal resistor 10% to 25% accurate 25% to 50% accurate tpg 21 05sr3.book page 3 thursday, august 4, 2005 1:08 pm
freescale 2-4 mc68hc05sr3 pin descriptions 2 2.2.3 rc oscillator option this configuration is intended to be the lowest cost option in applications where oscillator accuracy is not important. an internal constant current source and a capac itor have been integrated on-chip, connected between the osc2 pin and vss. thus by either connecting a resistor to vdd from osc2 or by putting a wire strap between osc1 and osc2 self-oscillations at the frequency as shown in figure 2-2 and figure 2-3 can be induced. figure 2-2 typical oscillator frequency for selected external resistor figure 2-3 typical oscillator frequency for wire-strap connection 60 30 40 50 70 90 100 110 80 4.0 3.5 3.0 2.5 2.0 1.5 resistance (k ? ) oscillator frequency (mhz) 3.5 2.0 2.5 3.0 4.0 5.0 5.5 6.0 4.5 2.25 2.00 1.75 1.50 1.25 1.00 vdd (v) oscillator frequency (mhz) t=0 c t=25 c t=50 c tpg 22 05sr3.book page 4 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale 2-5 pin descriptions 2 2.3 pin assignments figure 2-4 pin assignment for 40-pin pdip 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 vss reset irq vdd osc1 osc2 vpp timer pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd7 pd6/irq2 pd5/vrh pd4/vrl pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pd0/an0 pd1/an1 pd2/an2 pd3/an3 tpg 23 05sr3.book page 5 thursday, august 4, 2005 1:08 pm
freescale 2-6 mc68hc05sr3 pin descriptions 2 figure 2-5 pin assignment for 42-pin sdip figure 2-6 pin assignment for 44-pin qfp 42 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 vss(int) vss(ext) reset irq vdd osc1 osc2 vpp timer pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd7 pd6/irq2 pd5/vrh pd4/vrl nc pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pd0/an0 pd1/an1 pd2/an2 pd3/an3 nc pb1 pb3 12 13 15 16 17 18 19 20 21 22 14 33 32 30 29 28 27 26 25 24 23 31 vdd vss pd0/an0 pd1/an1 pd2/an2 pd3/an3 pd4/vrl pd5/vrh pd6/irq2 pd7 pb0 pa3 pa4 pa6 pa7 vss(int) vss(ext) reset irq vdd osc1 pa5 osc2 vpp pc0 pc1 pc2 pc3 pc5 pc6 pc7 timer pa2 pa1 pb7 pb6 pb5 pb4 pb2 pa0 1 2 4 5 6 7 8 9 10 11 3 pc4 44 43 41 40 39 38 36 35 34 42 37 tpg 24 05sr3.book page 6 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale 3-1 input/output ports 3 3 input/output ports the mc68hc05sr3 has 32 bidirectional i/o lines, arranged as four 8-bit i/o ports (port a, b, c, and d). the individual bits in these ports ar e programmable as eith er inputs or outputs under software control by the data direction register s (ddrs). all port pins each has an associated 20k ? pull-up resistor, which can be connected/di sconnected under software control. also, each port pin is capable of sinking and driving a maxi mum current of 10ma (e.g. direct drive for leds). port a can also be configured for keyboard interrupts. 3.1 parallel ports port a, b, c, and d are 8-bit bidirectional ports. each port pin is controlled by the corresponding bits in a data direction register and a data regi ster as shown in figure 3-1. the functions of the i/o pins are summarized in table 3-1. 3.1.1 port data registers each port i/o pin has a corresponding bit in the port data register. when a port i/o pin is programmed as an output the state of the corresponding data register bit determines the state of the output pin. all port i/o pins can drive a current of 10ma when programmed as outputs. when a port pin is programmed as an input, any read of the port data register will return the logic state of the corresponding i/o pin. the locations of t he data registers for port a, b, c, and d are at $00, $01, $02, and $03 respectively. the po rt data registers are unaffected by reset. table 3-1 i/o pin functions r/w ddr i/o pin function 0 0 the i/o pin is in input mode. data is written into the output data latch. 0 1 data is written into the output data latch and output to the i/o pin. 1 0 the state of the i/o pin is read. 1 1 the i/o pin is in an output mode. the output data latch is read. tpg 25 05sr3.book page 1 thursday, august 4, 2005 1:08 pm
freescale 3-2 mc68hc05sr3 input/output ports 3 3.1.2 port data direction registers each port pin may be programmed as an input by clearing the corresponding bit in the ddr, or programmed as an output by setting the corresp onding bit in the ddr. the ddr for port a, b, c, and d are located at $04, $05, $06 and, $07 respectively. the ddrs are cleared by reset. note: a ?glitch? may occur on an i/o pin when selecting from an input to an output unless the data register is first preconditioned to the desired state before changing the corresponding ddr bit from a ?0? to a ?1?. 3.2 port a ? keyboard interrupts (kbi) port a is configured for use as keyboard interrupts when the kbie bit is set in the miscellaneous control register (mcr). individual keyboard inte rrupt port pins are also maskable by setting corresponding bits in the keyboard interrupt mask register. see section 5.2.2.4 for details on the keyboard interrupts. 3.3 pd0:pd5 ? adc inputs when the adon bit is set in the adc status an d control register, pd0 to pd3 are configured as adc inputs an0 to an3 respectively. pd4 and pd5 are configured as v rl and v rh respectively. see section 7 for details on the analog to digital converter. figure 3-1 port i/o circuitry input register bit input i/o output i/o pin data direction register bit latched output data bit internal mc68hc05 connections tpg 26 05sr3.book page 2 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale 3-3 input/output ports 3 3.4 pd6 ? irq2 the port pin pd6 is configured as irq2 by setting the irq2e bit in the mcr. the external interrupt irq2 behaves similar to irq except it is edge-triggered only. see section 5.2.2.2 for details on the external interrupt irq2 . 3.5 programmable current drive all i/o ports, when programmed as outputs, can sour ce or sink a current of 10ma for driving leds directly. by setting the pil bit in the port opti on register (at $0a), pb5-pb7 can be programmed to a low-current mode that source or sink only a current of 2ma when programmed as output. this allows a direct drive to low current leds. note: although the ports each has high current drive capability, designs should limit the total port currents to not more than 100ma. figure 3-2 typical i ol vs v ol @v dd =5v 13 12 11 10 9 8 7 6 5 4 3 2 1 0 012345 all ports pb5-pb7 in low current mode worst case best case typical typical worst case best case v ol (volts) i ol (ma) tpg 27 05sr3.book page 3 thursday, august 4, 2005 1:08 pm
freescale 3-4 mc68hc05sr3 input/output ports 3 figure 3-3 typical i oh vs v oh @v dd =5v figure 3-4 typical i ol vs v ol @v dd =3v 0 ?1 ?2 ?3 ?4 ?5 ?6 ?7 ?8 ?9 ?10 ?11 ?12 ?13 012345 all ports pb5-pb7 in low current mode worst case best case typical typical worst case best case v oh (volts) i oh (ma) ?14 ?15 pb5-pb7 in low current mode worst case typical best case typical best case worst case all ports v ol (volts) i ol (ma) 0123 5 4 3 2 1 0 tpg 28 05sr3.book page 4 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale 3-5 input/output ports 3 3.6 programmable pull-up devices ports b, c, and d have 20k ? pull-up resistors, which can be connected or disconnected, by setting appropriate bits in the port option register (at $0a). 3.6.1 port option register pil ? pb5:pb7 current drive select 1 (set) ? pb5-pb7 are configured to 2ma drive port. 0 (clear) ? pb5-pb7 are configured to 10ma drive port. pdp ? port d pull-up 1 (set) ? the internal 20k ? pull-up resistors are c onnected to the inputs of port d. 0 (clear) ? no pull-up resistor is co nnected to the inputs of port d. figure 3-5 typical i ol vs v ol @v dd =3v address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port option register (popr) $0a pil pdp pcp pbp pb1 pb0 0000 0000 0 123 v oh (volts) 0 ?1 ?2 ?3 ?4 ?5 i oh (ma) pb5-pb7 in low current mode worst case typical best case typical best case worst case all ports tpg 29 05sr3.book page 5 thursday, august 4, 2005 1:08 pm
freescale 3-6 mc68hc05sr3 input/output ports 3 pcp ? port c pull-up 1 (set) ? the internal 20k ? pull-up resistors are connected to the inputs of port c. 0 (clear) ? no pull-up resistor is connected to the inputs of port c. pbp ? pb2:pb7 pull-up 1 (set) ? the internal 20k ? pull-up resistors are connected to the inputs of pb2-pb7. 0 (clear) ? no pull-up resistor is connected to the inputs of pb2-pb7. pb1 ? pb1 pull-up 1 (set) ? the internal 20k ? pull-up resistor is connected to the input of pb1. 0 (clear) ? no pull-up resistor is connected to the input of pb1. pb0 ? pb0 pull-up 1 (set) ? the internal 20k ? pull-up resistor is connected to the input of pb0. 0 (clear) ? no pull-up resistor is connected to the input of pb0. tpg 30 05sr3.book page 6 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale 4-1 memory and registers 4 4 memory and registers the mc68hc05sr3/ mc68hc705sr3 has 8k-bytes of addressable memory, consisting of i/o registers, user rom/ eprom , user ram, and self-check/ bootstrap rom . figure 4-1 shows the memory map for mc68hc05sr3/ mc68hc705sr3 device. 4.1 i/o registers the i/o, status and control registers are locat ed within the first 16 bytes of memory, from $0000 to $000f. these are shown in the memory map in figure 4-1; and a summary of the register outline is shown in table 4-1. reading from unim plemented bits will return unknown states, and writing to unimplemented bits will be ignored. 4.2 ram the user ram (including the stack) consists of 192 bytes. it is separated into two blocks at locations $0010 to $008f, and $00c0 to $00ff. the stack begins at address $00ff and proceeds down to $00c0. 4.3 rom the user rom consists of 3840 bytes of memory, from $1000 to $1eff. twelve bytes of user vectors are also available, from $1ff4 to $1fff. on the mc68hc705sr3, this rom is replaced by eprom. note: using the stack area for data storage or temporary work locations requires care to prevent the data from being overwritten due to stacking from an interrupt or subroutine call. tpg 31 05sr3.book page 1 thursday, august 4, 2005 1:08 pm
freescale 4-2 mc68hc05sr3 memory and registers 4 4.4 memory map figure 4-1 shows the memory map for mc68hc05sr3/ mc68hc705sr3 device. figure 4-1 mc68hc05sr3/ mc68hc705sr3 memory map eprom programming control register port a data register $00 $0000 port b data register $01 port c data register $02 port d data register $03 port a data direction register $04 port b data direction register $05 port c data direction register $06 port d data direction register $07 $08 $09 $0a $0b $0c $0d $0e $0f adc status and control register adc data register ports 8 bytes 0 15 user ram 128 bytes user rom/ eprom 3840 bytes $0010 $008f $0fff $0090 $1eff $1000 $1ff0 $1ff2 $1ff4 $1ff6 $1ff8 $1ffa $1ffc $1ffe i/o 16 bytes unused port option register eprom register reserved kbi irq2 irq swi reset $000f $00bf $00c0 stack 64 bytes $00ff $0100 unused user vectors 12 bytes $1fef $1ff0 $1fff $1f00 self-check/ bootstrap 240 bytes timer registers 2 bytes kbi register misc. register adc registers 2 bytes timer data register timer control register port option register keyboard interrupt mask register miscellaneous control register reserved timer tpg 32 05sr3.book page 2 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale 4-3 memory and registers 4 4.5 i/o registers summary table 4-1 shows a summary of i/o registers for mc68hc05sr3/ mc68hc705sr3 device. table 4-1 mc68hc05sr3/ mc68hc705sr3 i/o registers register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data $00 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 unaffected port b data $01 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 unaffected port c data $02 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 unaffected port d data $03 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 unaffected port a data direction $04 ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 0000 0000 port b data direction $05 ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 0000 0000 port c data direction $06 ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 0000 0000 port d data direction $07 ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 0000 0000 timer data (tdr) $08 td7 td6 td5 td4 td3 td2 td1 td0 1111 1111 timer control (tcr) $09 tif tim tcex tine prer pr2 pr1 pr0 0100 -000 port option (popr) $0a pil pdp pcp pbp pb1 pb0 --00 0000 kbi mask (kbim) $0b kbe7 kbe6 kbe5 kbe4 kbe3 kbe2 kbe1 kbe0 0000 0000 miscellaneous control (mcr) $0c kbie kbic into inte lvre sm irq2f irq2e 0001 0000 eprom programming control $0d elat pgm ---- --00 adc status and control (adscr) $0e coco adrc adon ch2 ch1 ch0 000- -000 adc data (addr) $0f ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 uuuu uuuu mask option (mor) $0fff smd sec tmr2 tmr1 tmr0 rc unaffected tpg 33 05sr3.book page 3 thursday, august 4, 2005 1:08 pm
freescale 4-4 mc68hc05sr3 memory and registers 4 this page left bl ank intentionally tpg 34 05sr3.book page 4 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale 5-1 resets and interrupts 5 5 resets and interrupts this section describes the reset and interrupt functions on the mcu. 5.1 resets the mc68hc05sr3 can be reset in three ways: by initial power-on re set function, (por), by an active low input to the reset pin, (reset ), and by a low voltage reset, (lvr). all of these resets will cause the program to go to the starting address, specified by the contents of memory locations $1ffe and $1fff, and cause the interrupt mask (i-bit ) of the condition code register (ccr) to be set. 5.1.1 power-on reset (por) the power-on reset (por) occurs on power-up to allow the clock oscillator to stabilize. the por is strictly for power-up conditions, and should not be used to detect any drops in power supply voltage. there is an oscillator stabilization delay of t porl internal processor bu s clock cycles after the oscillator becomes active. the reset pin will be pulled down internally during these cycles. if the reset pin is low (by external circuit) at the end of the t porl period, the processor remains in the reset conditi on until reset goes high. 5.1.2 reset pin the reset input pin is used to reset the mcu to provide an orderly software start-up procedure. when using the external reset, the reset pin must stay low for a minimum of 1.5t cyc . the reset pin is connected to a schmitt trigger circuit as part of its input to improve noise immunity. tpg 35 05sr3.book page 1 thursday, august 4, 2005 1:08 pm
freescale 5-2 mc68hc05sr3 resets and interrupts 5 5.1.3 low voltage reset (lvr) when the lvr function is enabled, an internal reset is generated if the supply voltage, v dd , drops below v lv r . (see section 11 for value of v lvr ). this lvr function is enabled by setting the lvre bit in the miscellaneous control register. lvre ? low voltage reset enable 1 (set) ? low voltage reset function enabled. 0 (clear) ? low voltage reset function disabled. note: the lvr function should not be enabled when operating v dd =3v. 5.2 interrupts the mc68hc05sr3 mcu can be interrupted by different sources ? four maskable hardware interrupt and one non-maskable software interrupt: software interrupt instruction (swi) external signal on irq pin external signal on irq2 pin timer overflow keyboard if the interrupt mask bit (i-bit) in the condition co de register (ccr) is set, all maskable interrupts are disabled. clearing the i-bit enables interrupts. interrupts cause the processor to save the regist er contents on the stack and to set the interrupt mask (i-bit) to prevent additional interrupts. the rti instruction causes th e register contents to be recovered from the stack and normal processing to resume. unlike reset, hardware interrupts do not cause th e current instruction execution to be halted, but are considered pending until the current instruction is complete. the current instruction is the one already fetched and being operated on. when the current instruction is complete, the processor checks all pending hardware interrupts. if interrupts are not masked (ccr i-bit clear) the processor proceeds with interrupt processing; ot herwise, the next instruction is fetched and executed. table 5-1 shows the relative priority of all the possible interrupt sources. figure 5-2 shows the interrupt processing flow. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset miscellaneous control register $0c kbie kbic into inte lvre sm irq2f irq2e 0001 0000 tpg 36 05sr3.book page 2 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale 5-3 resets and interrupts 5 5.2.1 non-maskable software interrupt (swi) the software interrupt (swi) is an executable instruction and a non-maskable interrupt: it is execute regardless of the state of the i-bit in the ccr. if the i-bit is zero (interrupt enabled), swi is executed after interrupts that were pending when the swi was fetched, but before interrupts generated after the swi was fetched. the swi inte rrupt service routine address is specified by the contents of memory locations $1ffc and $1ffd. figure 5-1 interrupt stacking order table 5-1 reset/interrupt vector addresses register flag name interrupt cpu interrupt vector address priority ? ? reset reset $1ffe-$1fff ? ? software swi $1ffc-$1ffd ? ? external interrupt irq $1ffa-$1ffb ? ? external interrupt 2 irq2 $1ff8-$1ff9 tcr tif timer overflow tif $1ff6-$1ff7 ? ? keyboard kbi $1ff4-$1ff5 condition code register accumulator index register program counter (high byte) program counter (low byte) ? ? ? ? ? ? ? ? ? ? ? ? $00c0 (bottom of stack) $00c1 $00c2 $00fd $00fe $00ff (top of stack) unstacking 1 2 3 4 5 5 4 3 2 1 stacking order order highest lowest tpg 37 05sr3.book page 3 thursday, august 4, 2005 1:08 pm
freescale 5-4 mc68hc05sr3 resets and interrupts 5 figure 5-2 hardware interrupt processing flowchart from reset is i-bit set? fetch next y n irq external y n interrupt ? timer interrupt? y n keyboard interrupt? y n instruction execute instruction clear external interrupt request latch pc (sp, sp?1) set i-bit in ccr load interrupt restore registers from stack cc, a, x, pc irq2 external y n interrupt ? x (sp?2) a (sp?3) cc (sp?4) vectors to swi instruction? y n rti instruction? y n program counter tpg 38 05sr3.book page 4 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale 5-5 resets and interrupts 5 5.2.2 maskable hard ware interrupts if the interrupt mask bit (i-bit) of the ccr is set, all maskable in terrupts are masked. clearing the i-bit allows interrupt processing to occur. note: the internal interrupt latch is cleared in th e first part of the interrupt service routine; therefore, one external interrupt pulse could be latched and serviced as soon as the i-bit is cleared. 5.2.2.1 external interrupt (irq ) the external interrupt irq is controlled by two bits in the miscellaneous control register ($0c). inte ? interrupt enable 1 (set) ? external interrupt irq is enabled. 0 (clear) ? external interrupt is disabled. the external irq is default enabled at power-on reset. into ? interrupt option 1 (set) ? negative-edge sensitive triggering for irq . 0 (clear) ? negative-level sensitive triggering for irq . when the signal of the external interrupt pin, irq , satisfies the condition selected, an external interrupt occurs. the actual processor interrupt is generated only if the interrupt mask bit of the condition code register is also cleared. when the interrupt is recognized, the current state of the processor is pushed onto the stack and the interr upt mask bit in the condition code register is set. this masks further interrupts until the present one is serviced. the service routine address is specified by the contents in $1ffa-$1ffb. the interrupt logic recognizes negative edge tr ansitions and pulses (special case of negative edges) on the external interrupt line. figure 5-3 shows both a block diagram and timing for the interrupt line (irq ) to the processor. the first method is used if pulses on the interrupt line are spaced far enough apart to be serviced. the minimum time between pulses is equal to the number of cycles required to execute the interrupt service routine plus 21 cycles. once a pulse occurs, the next pulse should not occur until the mcu softwar e has exited the routine (an rti occurs). the second configuration shows several interrupt lines wired-or to perform the interrupt at the processor. thus, if the interrupt lines remain low after servicing one interrupt, the next interrupt is recognized. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset miscellaneous control register $0c kbie kbic into inte lvre sm irq2f irq2e 0001 0000 tpg 39 05sr3.book page 5 thursday, august 4, 2005 1:08 pm
freescale 5-6 mc68hc05sr3 resets and interrupts 5 figure 5-3 external interrupt + & external request interrupt power-on reset external reset external interrupt being serviced (irq only) d c r q q v dd into bit i-bit (ccr) irq t ilih t ilil edge sensitive trigger condition the minimum pulse width t ilih is either 125ns (v dd =5v) or 250ns (v dd =3v). the period t ilil should not be less than the number of tcyc cycles it takes to ex- ecute the interrupt service routine plus 21 t cyc cycles. t ilih wired ored interrupt signals irq if after servicing an interrupt the external interrupt pin (irq ) remains low, then the next interrupt is recognized. normally used with pull-up resistors for wired-or connection. (b) interrupt mode diagram (a) interrupt function diagram level sensitive trigger condition + & & irq 100k v dd tpg 40 05sr3.book page 6 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale 5-7 resets and interrupts 5 5.2.2.2 external interrupt 2 (irq2 ) the port pin pd6 is configured as irq2 by setting the irq2e bit in the mcr. the external interrupt irq2 behaves similar to irq except it is edge-triggered only. irq2e ? irq2 enable 1 (set) ? external interrupt irq2 is enabled. 0 (clear) ? external interrupt irq2 is disabled. irq2f ? irq2 flag clear this is a write-only bit and always read as ?0?. 1 (set) ? writing a ?1? clears the irq2 interrupt latch. 0 (clear) ? writing a ?0? has no effect. when a negative-edge is sensed on irq2 pin, an external interrupt occurs. the actual processor interrupt is generated only if the i-bit in the ccr is also cleared. when the interrupt is recognized, the current state of the processor is pushed ont o the stack and the i-bit in the ccr is set. this masks further interrupts until the present one is serviced. the latch for irq2 is cleared by reset or by writing a ?1? to the irq2f bit in the mcr in the interrupt service routine. the interrupt service routine address is specified by the contents in $1ff8-$1ff9. 5.2.2.3 timer interrupt the timer interrupt is generated by the 8-bit timer when a timer overflow has occurred. the interrupt enable and flag for the timer interrupt are located in the timer control register. tim ? timer interrupt mask 1 (set) ? timer interr upt is disabled. 0 (clear) ? timer interrupt is enabled. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset miscellaneous control register $0c kbie kbic into inte lvre sm irq2f irq2e 0001 0000 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset timer control register (tcr) $09 tif tim tcex tine prep pr2 pr1 pr0 0100 -100 tpg 41 05sr3.book page 7 thursday, august 4, 2005 1:08 pm
freescale 5-8 mc68hc05sr3 resets and interrupts 5 tif ? timer interrupt flag 1 (set) ? a timer interrupt (t imer overflow) has occurred. 0 (clear) ? a timer interrupt (tim er overflow) has not occurred. the i-bit in the ccr must be cleared in order for th e timer interrupt to be processed. the interrupt will vector to the interrupt service routine at th e address specified by the contents in $1ff6-$0ff7. 5.2.2.4 keyboard interrupt (kbi) keyboard interrupt function is associated with port a pins. the keyboard interrupt function is enabled by setting the keyboard interrupt enable bit kbie (bit 7 of mcr at $0c) and the individual enable bits kbe0-kbe7 (bits 0-7 of kbim at $0b). when the kbex bit is set, the corresponding port a pin will be configured as an input pin, regardless of the ddr setting, and a 20k ? pull-up resistor is connected to the pin, as shown in figure 5-4. when a high to low transition is sensed on the pin, a keyboard interrupt will be generated. an interrupt to the cpu will be generated if the i-bit in the ccr is cleared. the keyboard interrupt flag should be cleared in the interrupt service routine (by writing a ?1? to kbic bit in the mcr at $0c) after the key is debounced. debouncing will avoid spurious false triggering. the keyboard interrupt is negative-edge sensitive only, and the interrupt service routine is specified by the cont ents in $1ff4-$1ff5. figure 5-4 keyboard interrupt circuitry pad logic & keyboard request interrupt v dd & & & kbex of kbim & kbie bit of mcr ($0c bit 7) ddr0-ddr7 internal data bit (0-7), port a pax 1 input for each of pa0-pa7 (8 input nand) 20k ? tpg 42 05sr3.book page 8 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale 5-9 resets and interrupts 5 the kbie bit in the miscellaneous control register controls the master enable for the keyboard interrupts. kbie ? keyboard interrupt enable 1 (set) ? keyboard interrupts master enabled. 0 (clear) ? keyboard interrupts master disabled. kbic ? keyboard interrupt clear this is a write-only bit and always read as ?0?. 1 (set) ? writing a ?1? clears the keyboard interrupt latch. 0 (clear) ? writing a ?0? has no effect. the keyboard interrupt mask register (kbimr) masks individual keyboard interrupt pins and setting of the internal pull-up resistors on port a. kbex ? pax keyboard interrupt enable 1 (set) ? keyboard interrupt enabled for pax. a 20k ? internal pull-up resistor is connected. high to low transition on pax will cause a keyboard interrupt. 0 (clear) ? keyboard interrupt for pax pin is masked. any transitions on pax will not set any flags. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset miscellaneous control register $0c kbie kbic into inte lvre sm irq2f irq2e 0001 0000 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset kbimr $0b kbe7 kbe6 kbe5 kbe4 kbe3 kbe2 kbe1 kbe0 0000 0000 tpg 43 05sr3.book page 9 thursday, august 4, 2005 1:08 pm
freescale 5-10 mc68hc05sr3 resets and interrupts 5 this page left bl ank intentionally tpg 44 05sr3.book page 10 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale 6-1 timer 6 6 timer this section describes the operation of the 8-bit count-down timer in the mc68hc05sr3. 6.1 timer overview the mc68hc05sr3 timer block diagram is shown in figure 6-1. the timer contains a single 8-bit software programmable count-down counter with a 7-bit software selectable prescaler. the counter may be preset under software control and decrements towards zero. when the counter decrements to zero, the timer interrupt flag (tif bit in timer control register, tcr) is set. once timer interrupt flag is set, an interrupt is generated to the cpu only if the tim bit in the tcr and i-bit in the ccr are cleared. when a interrupt is recognized, after completion of the current instruction, the processor proceeds to store the appropriate registers on the stack and then fetches the timer interrupt vector from locations $1ff6 and $1ff7. the counter continues to count after it reaches zero, allowing the software to determine the number of internal or external clocks since the timer interrupt flag was set. the counter may be read at any time by the processor without di sturbing the count. the c ontents of the counter become stable prior to the read portion of a cycle and do not change during the read. the timer interrupt flag remains set until cleared by the software. if a write occurs before the timer interrupt is served, the interrupt is lost. the timer interrupt flag may also be used as a scanned status bit in a non-interrupt mode of operation. the prescaler is a 7-bit divider which is used to extend the maximum length of the timer. bit 0, 1, 2 (pr0, pr1, pr2) of tcr are programmed to choose the appropriate prescaler output which is used as the 8-bit counter clock input. the processo r cannot write into or read from the prescaler; however, its contents can be cleared to all zeros by writing to the prer bit in the tcr. this will allow for truncation-free counting. the input clock for the timer sub-system is select able from internal, external, or a combination of internal and external sources. the tcex and tine bits in the timer control register selects the timer input clock. tpg 45 05sr3.book page 1 thursday, august 4, 2005 1:08 pm
freescale 6-2 mc68hc05sr3 timer 6 figure 6-1 timer block diagram clock source logic interrupt circuit timer data register ($08) tif tim tcex tine prer pr2 pr1 pr0 timer control register ($09) overflow detect circuit timer internal processor clock 8-bit count-down timer counter 7-bit prescaler counter prescaler select logic (8 to 1 mux) internal bus 8 8 8 8 rst tcex tine clock source 0 0 internal clock to timer 0 1 ?and? of internal clock and timer pin to timer 1 0 input clock to timer disabled 1 1 timer pin to timer tpg 46 05sr3.book page 2 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale 6-3 timer 6 6.2 timer control register (tcr) the tcr enables the software to control the operation of the timer. tif ? timer interrupt flag 1 (set) ? the timer has reached a count of zero. 0 (clear) ? the timer has not reached a count of zero. the timer interrupt flag is set when the 8-bit counter decrements to zero. this bit is cleared on reset, or by writing a ?0? to the tif bit. tim ? timer interrupt mask 1 (set) ? timer interrupt request to the cpu is masked (disabled). 0 (clear) ? timer interrupt request to the cpu is not masked (enabled). a reset sets this bit to one; it must then be clear ed by software to enable the timer interrupt to the cpu. this timer interrupt mask only masks timer interrupt request to the cpu, and does not affect counting of the 8-bit counter or the setting of tif. tcex ? timer clock external tine ? timer input enable these two bits selects the source of the timer cloc k. reset or power-on clears these bits to zero. prer ? prescaler reset writing a ?1? to this write-only bit will reset the prescaler to zero, which is necessary for any new counts set by writing to the timer data register .this bit always reads as zero, and is not affected by reset. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $09 tif tim tcex tine prer pre2 pre1 pre0 0100 -100 tcex tine clock source 00 internal clock to timer 01 ?and? of internal clock and timer pin to timer 10 input clock to timer disabled 11 timer pin to timer tpg 47 05sr3.book page 3 thursday, august 4, 2005 1:08 pm
freescale 6-4 mc68hc05sr3 timer 6 pr2:pr0 these three bits enable the program to select the division ratio of the prescaler. on reset, these three bits are set to ?100?, which corresponds to a division ratio of 16. 6.3 timer data register (tdr) the tdr is a read/write register which contains the current value of the 8-bit count-down timer counter when read. reading this register does not disturb the counter operation. 6.4 operation during low power modes the timer ceases counting in stop mode. when stop mode is exited by an external interrupt (irq or irq2 ), the internal oscillator will resume its operation, followed by internal processor stabilization delay. the timer is then cleared to zero and resumes its operation. the tif bit in the tcr will be set. to avoid generating a timer interrupt when exiting stop mode, it is recommended to set the tim bit prior entering stop mode. after exiting stop mode tif bit can then be cleared. the cpu clock halts during the wait mode, but the timer remains active. if the interrupts are enabled, the timer interrupt will cause the processor to exit the wait mode. pr2 pr1 pr0 divide ratio 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $08 td7 td6 td5 td4 td3 td2 td1 td0 1111 1111 tpg 48 05sr3.book page 4 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale 7-1 analog to digital converter 7 7 analog to digital converter the analog to digital converte r system consists of a single 8-bit successive approximation converter and an 8-channel analog multiplexer. four of the channels are available for analog inputs, and the other four channels are dedicated to internal test functions. there is one 8-bit adc data register ($0f) and one 8-bit adc status an d control register ($0e). the reference supply, v rl and v rh for the converter uses two input pins (sha red with pd4 and pd5) instead of the power supply lines, because drops caused by loading in the power supply lines would degrade the accuracy of the analog to digital conversion. an internal rc oscillator is available if the bus speed is low enough to degrade the adc accuracy. an adon bit allows the adc to be switched off to reduce power consumption, which is particularly useful in the wait mode. figure 7-1 adc converter block diagram ch2 ch1 ch0 coco adrc adon 8-bit capacitive dac with sample and hold successive approximation register and control result adc status and control register ($0e) analog mux (channel assignment) adc data register ($0f) vrh vrl an0 v rh (v rh +v rl )/2 v rl an1 an2 an3 (v rh +v rl )/4 8 tpg 49 05sr3.book page 1 thursday, august 4, 2005 1:08 pm
freescale 7-2 mc68hc05sr3 analog to digital converter 7 7.1 adc operation as shown in figure 7-1, the adc consists of an analog multiplexer, an 8-bit digital to analog capacitor array, a comparator and a successive approximation register (sar). there are eight options that can be selected by the multiplexer; the an0 to an3 input pins, v rh , v rl , (v rh +v rl )/4, or (v rh +v rl )/2. selection is done via the ch x bits in the adc status and control register. an0 to an3 are input points for adc conversion operations; the others are reference points which can be used for test purposes. the converter uses v rh and v rl as reference voltages. an input voltage equal to or greater than v rh converts to $ff. an input voltage equal to or less than v rl , but greater than v ss , converts to $00. maximum and minimum ratings must not be exceeded. each analog input source should use v rh as the supply voltage and should be referenced to v rl for the ratiometric conversions. to maintain full accuracy of the adc, the following should be noted: 1) v rh should be equal to or less than v cc ; 2) v rl should be equal to or greater than v ss but less than maximum specifications; and 3) v rh ?v rl should be equal to or greater than 4 volts. the adc reference inputs (v rh and v rl ) are applied to a precision internal digital to analog converter. control logic drives this d/a conver ter and the analog output is successively compared with the selected analog input sampled at the beginning of the conversion. the conversion is monotonic with no missing codes. the result of each successive comparison is stored in the successive approximation register (sar) and, when the conversion is complete, the contents of the sar are transferred to the read-only adc data register ($0f), and the co nversion complete flag, coco, is set in the adc status and control register ($0e). warning: any write to the adc status and control register will abort the current conversion, reset the conversion complete flag (coco) and a new conversion starts on the selected channel. at power-on or external reset, both the adrc and adon bits are cleared, thus the adc is disabled. tpg 50 05sr3.book page 2 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale 7-3 analog to digital converter 7 7.2 adc status and co ntrol register (adscr) the adscr is a read/write register containi ng status and control bits for the adc. coco ? conversion complete 1 (set) ? an adc conversion has completed; adc data register ($0f) contains valid conversion result. 0 (clear) ? adc conversion not completed. this read-only status bit is set when a conversi on is completed, indicating that the adc data register contains a valid result. this coco bit is cleared either by a write to the adscr or a read of the adc data register. once the coco bit is cleared, a new conversion automatically starts. if the coco bit is not cleared, conversions are initiated every 32 cycles. in this continuous conversion mode the adc data register is refreshed with new data, every 32 cycles, and the coco bit remains set. adrc ? adc rc oscillator control 1 (set) ? adc uses rc oscillator as clock source. 0 (clear) ? adc uses internal processor clock as clock source. the rc oscillator option must be used if the internal processor is running below 1mhz. a stabilization time of typically 1ms is requir ed when switching to the rc oscillator option. adon ? adc on 1 (set) ? adc is switched on. 0 (clear) ? adc is switched off. when the adc is turned from off to on, it requires a time t adon for the current sources to stabilize. during this time adc conversion resu lts may be inaccurate. switching the adc off disables the internal charge pump and rc oscillator (if selected by adrc=1), and hence saving power. ch2:ch0 ? channel select bits these three bits selects one of eight adc channels for the conversion. channels 0 to 3 correspond to inputs an0-an3 on port pins pd0-pd3 respectively. channels 4 and 5 are the adc reference inputs v rh and v rl , on port pins pd4 and pd5 respectively. channels 6 and 7 are used for internal reference points. table 7-1 shows the signals selected by the channel select bits. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $0e coco adrc adon ch2 ch1 ch0 000- -000 tpg 51 05sr3.book page 3 thursday, august 4, 2005 1:08 pm
freescale 7-4 mc68hc05sr3 analog to digital converter 7 using a port d pin as both an analog and digital input simultaneously is prohibited. when the adc is enabled (adon=1) and one of channels 0 to 5 is selected, the corresponding port d pin will appear as a logic zero when read from the port data register. 7.3 adc data register (addr) the addr stores the result of a valid adc co nversion when the coco bits is set in adscr. 7.4 adc during low power modes the adc continues normal operation in wait mode. to reduce power consumption in wait mode, the adon and adrc bits in the adscr shoul d be cleared if the adc is not used. if the adc is in use and the internal bus clock is ab ove 1mhz, it is recommended that the adrc bit be cleared. in stop mode, the adc stops operation. table 7-1 adc channel assignments ch2 ch1 ch0 channel selected signal 0 0 0 0 ad0 on pd0 0 0 1 1 ad1 on pd1 0 1 0 2 ad2 on pd2 0 1 1 3 ad3 on pd3 100 4 v rh 101 5 v rl 110 6 (v rh ?v rl ) 4 111 7 (v rh ?v rl ) 2 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $0f ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 uuuu uuuu tpg 52 05sr3.book page 4 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale 8-1 cpu core and instruction set 8 8 cpu core and instruction set this section provides a description of the cp u core registers, the instruction set and the addressing modes of the mc68hc05sr3. 8.1 registers the mcu contains five r egisters, as shown in the programmi ng model of figure 8-1. the interrupt stacking order is shown in figure 8-2. 8.1.1 accumulator (a) the accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. figure 8-1 programming model accumulator index register program counter stack pointer condition code register carry / borrow zero negative interrupt mask half carry 70 70 15 7 0 0 15 7 0 0 0 0 0 0 0 0 1 1 70 1 1 1 h i n z c tpg 53 05sr3.book page 1 thursday, august 4, 2005 1:08 pm
freescale 8-2 mc68hc05sr3 cpu core and instruction set 8 8.1.2 index register (x) the index register is an 8-bit register, which can contain the indexed addressing value used to create an effective address. the index register may also be used as a temporary storage area. 8.1.3 program counter (pc) the program counter is a 16-bit register, which contai ns the address of the next byte to be fetched. 8.1.4 stack pointer (sp) the stack pointer is a 16-bit register, which c ontains the address of the next free location on the stack. during an mcu reset or the reset stack point er (rsp) instruction, the stack pointer is set to location $00ff. the stack pointer is then decrem ented as data is pushed onto the stack and incremented as data is pulled from the stack. when accessing memory, the ten most significant bits are permanently set to 0000000011. these ten bits are appended to the six least significant register bits to produ ce an address within the range of $00c0 to $00ff. subroutines and interrupt s may use up to 64 (decimal) locations. if 64 locations are exceeded, the stack pointer wrap s around and overwrites the previously stored information. a subroutine call occupies two locations on the stack; an interrupt uses five locations. 8.1.5 condition code register (ccr) the ccr is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the fifth bit indicates whether interrupts are masked. these bits can be individually tested by a program, and specific actions can be taken as a result of their state. each bit is explained in the following paragraphs. half carry (h) this bit is set during add and adc operations to indicate that a carry occurred between bits 3 and 4. figure 8-2 stacking order condition code register accumulator index register program counter high program counter low 70 stack unstack decreasing memory address increasing memory address interrupt return tpg 54 05sr3.book page 2 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale 8-3 cpu core and instruction set 8 interrupt (i) when this bit is set, all maskable interrupts are ma sked. if an interrupt occurs while this bit is set, the interrupt is latched and remains pending until the interrupt bit is cleared. negative (n) when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. zero (z) when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. carry/borrow (c) when set, this bit indicates that a carry or borrow out of the arithmetic logical unit (alu) occurred during the last arithmetic operation. this bit is also affected during bit test and branch instructions and during shifts and rotates. 8.2 instruction set the mcu has a set of 62 basic instructions. th ey can be grouped into five different types as follows: ? register/memory ? read/modify/write ?branch ? bit manipulation ? control the following paragraphs briefly explain each ty pe. all the instructions within a given type are presented in individual tables. this mcu uses all the instructions available in the m146805 cmos family plus one more: the unsigned multiply (mul) instruction. this instruct ion allows unsigned multiplication of the contents of the accumulator (a) and the index register (x). the high-order product is then stored in the index register and the low-order product is stored in the accumulator. a detailed definition of the mul instruction is shown in table 8-1. tpg 55 05sr3.book page 3 thursday, august 4, 2005 1:08 pm
freescale 8-4 mc68hc05sr3 cpu core and instruction set 8 8.2.1 register/memory instructions most of these instructions use two operands. the first operand is either the accumulator or the index register. the second operand is obtained from memory using one of the addressing modes. the jump unconditional (jmp) and jump to su broutine (jsr) instructions have no register operand. refer to table 8-2 for a complete list of register/memory instructions. 8.2.2 branch instructions these instructions cause the program to branch if a particular condition is met; otherwise, no operation is performed. branch instructions ar e two-byte instructions. refer to table 8-3. 8.2.3 bit manipulation instructions the mcu can set or clear any writable bit that re sides in the first 256 bytes of the memory space (page 0). all port data and data direction regist ers, timer and serial interface registers, control/status registers and a po rtion of the on-chip ram reside in page 0. an additional feature allows the software to test and branch on the stat e of any bit within these locations. the bit set, bit clear, bit test and branch functions are all impl emented with single instructions. for the test and branch instructions, the value of the bit tested is also placed in the carry bit of the condition code register. refer to table 8-4. 8.2.4 read/modify/write instructions these instructions read a memory location or a r egister, modify or test it s contents, and write the modified value back to memory or to the register. the test for negative or zero (tst) instruction is an exception to this sequence of reading, modifyin g and writing, since it does not modify the value. refer to table 8-5 for a complete list of read/modify/write instructions. 8.2.5 control instructions these instructions are register reference instru ctions and are used to control processor operation during program execution. refer to table 8-6 fo r a complete list of control instructions. 8.2.6 tables tables for all the instruction types listed above follow. in addition there is a complete alphabetical listing of all the instructions (see table 8-7), and an opcode map for the instruction set of the m68hc05 mcu family (see table 8-8). tpg 56 05sr3.book page 4 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale 8-5 cpu core and instruction set 8 table 8-1 mul instruction operation x:a x*a description multiplies the eight bits in the index register by the eight bits in the accumulator and places the 16-bit result in the concatenated accumulator and index register. condition codes h : cleared i : not affected n : not affected z : not affected c : cleared source mul form addressing mode cycles bytes opcode inherent 11 1 $42 table 8-2 register/memory instructions addressing modes immediate direct extended indexed (no offset) indexed (8-bit offset) indexed (16-bit offset) function mnemonic opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles load a from memory lda a6 2 2 b6 2 3 c6 3 4 f6 1 3 e6 2 4 d6 3 5 load x from memory ldx ae 2 2 be 2 3 ce 3 4 fe 1 3 ee 2 4 de 3 5 store a in memory sta b724c735f714e725d736 store x in memory stx bf24cf35ff14ef25df36 add memory to a addab22bb23cb34fb13eb24db35 add memory and carry to a adca922b923c934f913e924d935 subtract memory suba02 2b02 3c03 4f01 3e02 4d03 5 subtract memory from a with borrow sbca22 2b22 3c23 4f21 3e22 4d23 5 and memory with a anda422b423c434f413e424d435 or memory with a oraaa22ba23ca34fa13ea24da35 exclusive or memory with a eora822b823c834f813e824d835 arithmetic compare a with memory cmpa12 2b12 3c13 4f11 3e12 4d13 5 arithmetic compare x with memory cpxa32 2b32 3c33 4f31 3e32 4d33 5 bit test memory with a (logical compare) bit a52 2b52 3c53 4f51 3e52 4d53 5 jump unconditional jmp bc22cc33fc12ec23dc34 jump to subroutine jsr bd25cd36fd15ed26dd37 tpg 57 05sr3.book page 5 thursday, august 4, 2005 1:08 pm
freescale 8-6 mc68hc05sr3 cpu core and instruction set 8 table 8-3 branch instructions relative addressing mode function mnemonic opcode # bytes # cycles branch always bra 20 2 3 branch never brn 21 2 3 branch if higher bhi 22 2 3 branch if lower or same bls 23 2 3 branch if carry clear bcc 24 2 3 (branch if higher or same) (bhs) 24 2 3 branch if carry set bcs 25 2 3 (branch if lower) (blo) 25 2 3 branch if not equal bne 26 2 3 branch if equal beq 27 2 3 branch if half carry clear bhcc 28 2 3 branch if half carry set bhcs 29 2 3 branch if plus bpl 2a 2 3 branch if minus bmi 2b 2 3 branch if interrupt mask bit is clear bmc 2c 2 3 branch if interrupt mask bit is set bms 2d 2 3 branch if interrupt line is low bil 2e 2 3 branch if interrupt line is high bih 2f 2 3 branch to subroutine bsr ad 2 6 table 8-4 bit manipulation instructions addressing modes bit set/clear bit test and branch function mnemonic opcode # bytes # cycles opcode # bytes # cycles branch if bit n is set brset n (n=0?7) 2?n 3 5 branch if bit n is clear brclr n (n=0?7) 01+2?n 3 5 set bit n bset n (n=0?7) 10+2?n 2 5 clear bit n bclr n (n=0?7) 11+2?n 2 5 tpg 58 05sr3.book page 6 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale 8-7 cpu core and instruction set 8 table 8-5 read/modify/write instructions addressing modes inherent (a) inherent (x) direct indexed (no offset) indexed (8-bit offset) function mnemonic opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles increment inc 4c1 35c1 33c2 57c1 56c2 6 decrement dec4a1 35a1 33a2 57a1 56a2 6 clear clr4f1 35f1 33f2 57f1 56f2 6 complement com431 3531 3332 5731 5632 6 negate (two?s complement) neg 40 1 3 50 1 3 30 2 5 70 1 5 60 2 6 rotate left through carry rol 49 1 3 59 1 3 39 2 5 79 1 5 69 2 6 rotate right through carry ror461 3561 3362 5761 5662 6 logical shift left lsl 481 3581 3382 5781 5682 6 logical shift right lsr 44 1 3 54 1 3 34 2 5 74 1 5 64 2 6 arithmetic shift right asr 47 1 3 57 1 3 37 2 5 77 1 5 67 2 6 test for negative or zero tst4d1 35d1 33d2 47d1 46d2 5 multiply mul 42 1 11 table 8-6 control instructions inherent addressing mode function mnemonic opcode # bytes # cycles transfer a to x tax 97 1 2 transfer x to a txa 9f 1 2 set carry bit sec 99 1 2 clear carry bit clc 98 1 2 set interrupt mask bit sei 9b 1 2 clear interrupt mask bit cli 9a 1 2 software interrupt swi 83 1 10 return from subroutine rts 81 1 6 return from interrupt rti 80 1 9 reset stack pointer rsp 9c 1 2 no-operation nop 9d 1 2 stop stop 8e 1 2 wait wait 8f 1 2 tpg 59 05sr3.book page 7 thursday, august 4, 2005 1:08 pm
freescale 8-8 mc68hc05sr3 cpu core and instruction set 8 table 8-7 instruction set mnemonic addressing modes condition codes inh imm dir ext rel ix ix1 ix2 bsc btb h i n z c adc ? ? ??? add ? ? ??? and ?? ?? ? asl ?? ??? asr ?? ??? bcc ????? bclr ????? bcs ????? beq ????? bhcc ????? bhcs ????? bhi ????? bhs ????? bih ????? bil ????? bit ?? ?? ? blo ????? bls ????? bmc ????? bmi ????? bms ????? bne ????? bpl ????? bra ????? brn ????? brclr ???? ? brset ???? ? bset ????? bsr ????? clc ????0 cli ?0??? clr ??01? cmp ? ? ??? condition code symbols h half carry (from bit 3) ? tested and set if true, cleared otherwise i interrupt mask ? not affected n negate (sign bit) ? load ccr from stack z zero 0 cleared c carry/borrow 1 set not implemented address mode abbreviations bsc bit set/clear imm immediate btb bit test & branch ix indexed (no offset) dir direct ix1 indexed, 1 byte offset ext extended ix2 indexed, 2 byte offset inh inherent rel relative tpg 60 05sr3.book page 8 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale 8-9 cpu core and instruction set 8 com ?? ?? 1 cpx ?? ??? dec ?? ?? ? eor ?? ?? ? inc ?? ?? ? jmp ????? jsr ????? lda ?? ?? ? ldx ?? ?? ? lsl ?? ??? lsr ??0 ?? mul 0???0 neg ?? ??? nop ????? ora ?? ?? ? rol ?? ??? ror ?? ??? rsp ????? rti ????? rts ????? sbc ?? ??? sec ????1 sei ?1??? sta ?? ?? ? stop ?0??? stx ?? ?? ? sub ?? ??? swi ?1??? tax ????? tst ?? ?? ? txa ????? wait ?0??? table 8-7 instruction set (continued) mnemonic addressing modes condition codes inh imm dir ext rel ix ix1 ix2 bsc btb h i n z c condition code symbols h half carry (from bit 3) ? tested and set if true, cleared otherwise i interrupt mask ? not affected n negate (sign bit) ? load ccr from stack z zero 0 cleared c carry/borrow 1 set not implemented address mode abbreviations bsc bit set/clear imm immediate btb bit test & branch ix indexed (no offset) dir direct ix1 indexed, 1 byte offset ext extended ix2 indexed, 2 byte offset inh inherent rel relative tpg 61 05sr3.book page 9 thursday, august 4, 2005 1:08 pm
freescale 8-10 mc68hc05sr3 cpu core and instruction set 8 table 8-8 m68hc05 opcode map bit manipulation branch read/modify/write control register/memory btb bsc rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix high 0123456789abcdef high low 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 low 0 0000 553533659 234543 0 0000 brset0 bset0 bra neg nega negx neg neg rti sub sub sub sub sub sub 3btb2bsc2rel2dir1inh1inh2 ix11 ix1inh 2imm2 dir3ext3 ix22 ix11 ix 1 0001 553 6 234543 1 0001 brclr0 bclr0 brn rts cmpcmpcmpcmpcmpcmp 3 btb 2 bsc 2 rel 1inh 2imm2 dir3ext3 ix22 ix11 ix 2 0010 553 11 234543 2 0010 brset1 bset1 bhi mul sbc sbc sbc sbc sbc sbc 3 btb 2 bsc 2 rel 1inh 2imm2 dir3ext3 ix22 ix11 ix 3 0011 5535336510 234543 3 0011 brclr1 bclr1 bls com coma comx com com swi cpxcpxcpxcpxcpxcpx 3btb2bsc2rel2dir1inh1inh2 ix11 ix1inh 2imm2 dir3ext3 ix22 ix11 ix 4 0100 55353365 234543 4 0100 brset2 bset2 bcc lsr lsra lsrx lsr lsr and and and and and and 3btb2bsc2rel2dir1inh1inh2 ix11 ix 2imm2 dir3ext3 ix22 ix11 ix 5 0101 553 234543 5 0101 brclr2 bclr2 bcs bitbitbitbitbitbit 3 btb 2 bsc 2 rel 2imm2 dir3ext3 ix22 ix11 ix 6 0110 55353365 234543 6 0110 brset3 bset3 bne ror rora rorx ror ror lda lda lda lda lda lda 3btb2bsc2rel2dir1inh1inh2 ix11 ix 2imm2 dir3ext3 ix22 ix11 ix 7 0111 55353365 2 45654 7 0111 brclr3 bclr3 beq asr asra asrx asr asr tax sta sta sta sta sta 3btb2bsc2rel2dir1inh1inh2 ix11 ix 1inh 2dir3ext3ix22ix11 ix 8 1000 55353365 2234543 8 1000 brset4 bset4 bhcc lsl lsla lslx lsl lsl clc eor eor eor eor eor eor 3btb2bsc2rel2dir1inh1inh2 ix11 ix 1inh2imm2dir3ext3 ix22 ix11 ix 9 1001 55353365 2234543 9 1001 brclr4 bclr4 bhcs rol rola rolx rol rol sec adc adc adc adc adc adc 3btb2bsc2rel2dir1inh1inh2 ix11 ix 1inh2imm2dir3ext3 ix22 ix11 ix a 1010 55353365 2234543 a 1010 brset5 bset5 bpl dec deca decx dec dec cli ora ora ora ora ora ora 3btb2bsc2rel2dir1inh1inh2 ix11 ix 1inh2imm2dir3ext3 ix22 ix11 ix b 1011 553 2234543 b 1011 brclr5 bclr5 bmi sei add add add add add add 3 btb 2 bsc 2 rel 1inh2imm2dir3ext3 ix22 ix11 ix c 1100 55353365 2 23432 c 1100 brset6 bset6 bmc inc inca incx inc inc rsp jmp jmp jmp jmp jmp 3btb2bsc2rel2dir1inh1inh2 ix11 ix 1inh 2dir3ext3ix22ix11 ix d 1101 55343354 2656765 d 1101 brclr6 bclr6 bms tst tsta tstx tst tst nop bsr jsr jsr jsr jsr jsr 3btb2bsc2rel2dir1inh1inh2 ix11 ix 1 inh 2 rel 2 dir 3 ext 3 ix2 2 ix1 1 ix e 1110 553 2 234543 e 1110 brset7 bset7 bil stop ldx ldx ldx ldx ldx ldx 3 btb 2 bsc 2 rel 1inh 2imm2 dir3ext3 ix22 ix11 ix f 1111 5535336522 45654 f 1111 brclr7 bclr7 bih clr clra clrx clr clr wait txa stx stx stx stx stx 3btb2bsc2rel2dir1inh1inh2 ix11 ix1inh1inh 2dir3ext3ix22ix11 ix f 1111 3 0 0000 sub 1ix opcode in hexadecimal opcode in binary address mode cycles bytes mnemonic legend abbreviations for address modes and registers bsc btb dir ext inh imm ix ix1 ix2 rel a x bit set/clear bit test and branch direct extended inherent immediate indexed (no offset) indexed, 1 byte (8-bit) offset indexed, 2 byte (16-bit) offset relative accumulator index register not implemented tpg 62 05sr3.book page 10 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale 8-11 cpu core and instruction set 8 8.3 addressing modes ten different addressing modes provide programmer s with the flexibility to optimize their code for all situations. the various indexed addressing modes make it possible to locate data tables, code conversion tables and scaling tables anywhere in the memory space. short indexed accesses are single byte instructions; the longest instructions (three bytes) enable access to tables throughout memory. short absolute (direct) and long absolute (extended) addressing are also included. one or two byte direct addressing instructions ac cess all data bytes in most applications. extended addressing permits jump instructions to reach all memory locations. the term ?effective address? (ea) is used in describing the various addressing modes. the effective address is defined as the address from wh ich the argument for an instruction is fetched or stored. the ten addressing modes of the processor are described below. parentheses are used to indicate ?contents of? the location or register referred to. for example, (pc) indicates the contents of the location pointed to by the pc (p rogram counter). an arrow indicates ?is replaced by? and a colon indicates concatenation of two bytes. for additional details and graphical illustrations, refer to the m6805 hmos/m146805 cmos family microcomputer/ microprocessor user's manual or to the m68hc05 applications guide . 8.3.1 inherent in the inherent addressing mode, all the info rmation necessary to execute the instruction is contained in the opcode. operations specifying on ly the index register or accumulator, as well as the control instruction, with no other arguments are included in this mode. these instructions are one byte long. 8.3.2 immediate in the immediate addressing mode, the operand is contained in the byte immediately following the opcode. the immediate addressing mode is used to access constants that do not change during program execution (e.g. a constant used to initialize a loop counter). ea = pc+1; pc pc+2 8.3.3 direct in the direct addressing mode, the effective addre ss of the argument is contained in a single byte following the opcode byte. direct addressing allows the user to directly address the lowest 256 bytes in memory with a single two-byte instruction. ea = (pc+1); pc pc+2 address bus high 0; address bus low (pc+1) tpg 63 05sr3.book page 11 thursday, august 4, 2005 1:08 pm
freescale 8-12 mc68hc05sr3 cpu core and instruction set 8 8.3.4 extended in the extended addressing mode, the effective addr ess of the argument is contained in the two bytes following the opcode byte. instructions with extended addressing mode are capable of referencing arguments anywhere in memory with a single three-byte instruction. when using the freescale assembler, the user need not specify whether an instruction uses direct or extended addressing. the assembler automatically sele cts the short form of the instruction. ea = (pc+1):(pc+2); pc pc+3 address bus high (pc+1); address bus low (pc+2) 8.3.5 indexed, no offset in the indexed, no offset addressing mode, the ef fective address of the argument is contained in the 8-bit index register. this addressing mode can access the first 256 memory locations. these instructions are only one byte long. this mode is often used to move a pointer through a table or to hold the address of a frequently referenced ram or i/o location. ea = x; pc pc+1 address bus high 0; address bus low x 8.3.6 indexed, 8-bit offset in the indexed, 8-bit offset addressing mode, t he effective address is the sum of the contents of the unsigned 8-bit index register and the unsig ned byte following the opcode. therefore the operand can be located anywhere within the lowest 511 memory locations. this addressing mode is useful for selecting the mth element in an n element table. ea = x+(pc+1); pc pc+2 address bus high k; address bus low x+(pc+1) where k = the carry from the addition of x and (pc+1) 8.3.7 indexed, 16-bit offset in the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the two un signed bytes following the opcode. this address mode can be used in a manner similar to indexed, 8- bit offset except that th is three-byte instruction allows tables to be anywhere in memory. as with direct and extended addressing, the freescale assembler determines the shortest form of indexed addressing. ea = x+[(pc+1):(pc+2)]; pc pc+3 address bus high (pc+1)+k; address bus low x+(pc+2) where k = the carry from the addition of x and (pc+2) tpg 64 05sr3.book page 12 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale 8-13 cpu core and instruction set 8 8.3.8 relative the relative addressing mode is only used in branch instructions. in relative addressing, the contents of the 8-bit signed byte (the offset) following the opcode are added to the pc if, and only if, the branch conditions are true. otherwise, cont rol proceeds to the next instruction. the span of relative addressing is from ?126 to +129 from the opcode address. the programmer need not calculate the offset when using the freescale assemb ler, since it calculates the proper offset and checks to see that it is wit hin the span of the branch. ea = pc+2+(pc+1); pc ea if branch taken; otherwise ea = pc pc+2 8.3.9 bit set/clear in the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode. the byte following the opcode specifies the address of the byte in which the specified bit is to be set or cleared. any read/write bit in the first 256 locations of memory, including i/o, can be selectively set or cleared with a single two-byte instruction. ea = (pc+1); pc pc+2 address bus high 0; address bus low (pc+1) 8.3.10 bit test and branch the bit test and branch addressing mode is a combination of direct addressing and relative addressing. the bit to be tested and its condition (set or clear) is included in the opcode. the address of the byte to be tested is in the si ngle byte immediately following the opcode byte (ea1). the signed relative 8-bit offset in the third byte ( ea2) is added to the pc if the specified bit is set or cleared in the specified memory location. this single three-byte instruction allows the program to branch based on the condition of any readable bit in the first 256 locations of memory. the span of branch is from ?125 to +130 from the op code address. the state of the tested bit is also transferred to the carry bit of the condition code register. ea1 = (pc+1); pc pc+2 address bus high 0; address bus low (pc+1) ea2 = pc+3+(pc+2); pc ea2 if branch taken; otherwise pc pc+3 tpg 65 05sr3.book page 13 thursday, august 4, 2005 1:08 pm
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mc68hc05sr3 freescale 9-1 low power modes 9 9 low power modes the mc68hc05sr3 has three low-power operatin g modes. the wait and stop instructions provide two modes that reduce the power required for the mcu by stopping various internal clocks and/or the on-chip oscillator. the flow of the st op and wait modes is shown in figure 9-1. the third low-power operating mode is the slow mode. 9.1 stop mode execution of the stop instruction places the m cu in its lowest power consumption mode. in the stop mode the internal oscillator is turned off, halting all internal processing. when the cpu enters stop mode the i-bit in the condition code register is cleared automatically, so that any hardware interrupts (irq , irq2 and kbi) can ?wake? the mcu. all other registers and memory contents remain unalter ed. all input/output lines remain unchanged. the mcu can be brought out of the stop mode only by a hardware interrupt or an externally generated reset. when exiting the stop mode t he internal oscillator will resume after a pre-defined number of internal processor clock cycles, due to oscillator stabilization. 9.2 wait mode the wait instruction places the mcu in a low-power mode, but consumes more power than the stop mode. in the wait mode the internal proc essor clock is halted, su spending all processor and internal bus activities. other internal clocks remain active, permitting interrupts to be generated from the timer. the timer may be used to generate a periodic exit from the wait mode or, in conjunction with the external timer pin, on the occurrence of external events. execution of the wait instruction automatically clears the i-bit in the condition code register, so that any hardware interrupt can ?wake? the mcu. all other registers, memory, and input/output lines remain in their previous states. tpg 67 05sr3.book page 1 thursday, august 4, 2005 1:08 pm
freescale 9-2 mc68hc05sr3 low power modes 9 figure 9-1 stop and wait mode flowcharts stop n y wait fetch reset vector or service interrupt (a) (b) (c) stack set i-bit vector to interrupt routine external reset? external hardware interrupt? keyboard interrupt? y y y n n restart internal processor clock n timer interrupt? y n stop internal processor clock, clear i-bit in ccr external oscillator active, and internal timer clock active reset external oscillator, and stabilization delay end of start-up delay? y n y n stop internal processor clock, clear i-bit in ccr stop external oscillator, stop internal timer clock, and reset start-up delay external hardware interrupt? external reset? tpg 68 05sr3.book page 2 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale 9-3 low power modes 9 9.3 slow mode the slow mode function is controlled by the sm bit in the miscellaneous control register. when the sm bit is set, the internal bus clock is divi ded by 16, resulting to a frequency equal to the oscillator frequency divide by 32. this feature per mits a slow down of all the internal operations and thus reduces power consumption ? particularl y useful while in wait mode. the sm bit is automatically cleared while going to stop mode. sm ? slow mode 1 (set) ? slow mode enabled. internal bus frequency f op =f osc 32. 0 (clear) ? slow mode disabled. internal bus frequency f op =f osc 2. 9.4 data-retention mode if the low voltage reset function is not enable d, the contents of ram and cpu registers are retained at supply voltages as low as 2vdc. th is is called the data-retention mode where the data is held, but the devi ce is not guar anteed to operate. the reset pin must be held low during data-retention mode. the low voltage reset function is enabled/disabl ed by the lvre bit in the miscellaneous control register ($0c). lvre ? low voltage reset enable 1 (set) ? low voltage reset function enabled. 0 (clear) ? low voltage reset function disabled. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset miscellaneous control register $0c kbie kbic into inte lvre sm irq2f irq2e 0001 0000 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset miscellaneous control register $0c kbie kbic into inte lvre sm irq2f irq2e 0001 0000 tpg 69 05sr3.book page 3 thursday, august 4, 2005 1:08 pm
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mc68hc05sr3 freescale 10-1 operating modes 10 10 operating modes the mc68hc05sr3/ mc68hc705sr3 has two modes of operation: the user mode and the self-check/ bootstrap mode. table 10-1 shows the conditions required for entering the two operating modes. 10.1 user mode the normal operating mode of the mc68hc05sr3/ mc68hc705sr3 is the user mode. this mode is entered on the rising edge of reset when the v pp and pb1 pins are between v ss and v dd . 10.2 self-check mode the self-check mode is provided on the mc68hc05s r3 for the user to check device functions with an on-chip self-check program masked at location $1f00 to $1fef under minimum hardware support. the self-check schematic is shown in figure 10-1. self-check mode is entered on the rising edge of reset when the v pp pin is at v tst (2 v dd ) and pb1 pin is at v dd . once in the self-check mode, pb1 can then be used for other purposes. after entering the self-check mode, cpu branches to the self-check program and carries out the self-check. self-check is a repetitive test, i.e. if all parts are checked to be good, the cpu will repeat the self-check again. therefore, the leds attached to port a will be flashing if th e device is good; else the combination of leds? on-off pattern can show what part of the device is suspected to be bad. table 10-2 lists the leds? on-off patterns and their corresponding indications. table 10-1 mode selection reset v pp pb1 mode v ss to v dd v ss to v dd user v tst v dd self-check/ bootstrap v tst =2 v dd 5v tpg 71 05sr3.book page 1 thursday, august 4, 2005 1:08 pm
freescale 10-2 mc68hc05sr3 operating modes 10 figure 10-1 mc68hc05sr3 self-check circuit osc1 osc2 mc68hc05sr3 4mhz +5v 330 330 reset irq +5v vss 330 330 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb4 pb1 pb5 pb2 pb6 pb7 1 f 4k7 + reset vdd +5v pb3 out +5v pd0/an0 pd1/an1 pd2/an2 pd3/an3 pd4/vrl pd5/vrh pd6/irq2 pd7 timer vpp + vpp 47 f 0.1 f crystal osc 10k d4 d3 d2 d1 tpg 72 05sr3.book page 2 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale 10-3 operating modes 10 10.3 bootstrap mode the bootstrap mode is provided in the eprom part (mc68hc705sr3) as a mean of self-programming its eprom with minimal circuitry. bootstrap mode will be entered on the rising edge of reset when the v pp pin is at v tst (2 v dd ) and pb1 pin is at v dd . once in the bootstrap mode, pb1 can then be used for other purpos es. after entering the bootstrap mode, cpu branches to the bootstrap program and carries out the eprom programming routine. the user eprom consists of 3840 bytes, from location $1000 to $1eff. refer to appendix a for further details on mc68hc705sr3. table 10-2 self-check report d4 d3 d2 d1 remarks flashing o.k. (self- check is on-going) 1 1 1 1 bad port a 1 1 1 0 bad port b 1 1 0 1 bad port c 1 1 0 0 bad port d 1011 bad ram 1010 bad rom 1000 bad swi 0111 bad irq 1=led on, 0=led off tpg 73 05sr3.book page 3 thursday, august 4, 2005 1:08 pm
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mc68hc05sr3 freescale 11-1 electrical specifications 11 11 electrical specifications this section contains the electrical specifications for mc68hc05sr3. 11.1 maximum ratings this device contains circuitry to protect the i nputs against damage due to high static voltages or electric fields. however, it is advised that norma l precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this high impedance circuit. for proper operation it is recommended that vin and vout be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g. either v ss or v dd ). 11.2 thermal characteristics (voltages referenced to v ss ) ratings symbol value unit supply voltage v dd ?0.3 to +7.0 v input voltage v in v ss ?0.3 to v dd +0.3 v v pp pin v in v ss ?0.3 to 2xv dd +0.3 v current drain per pin excluding v dd and v ss i d 25 ma operating temperature standard extended t a t l to t h 0 to +70 ?40 to +85 c storage temperature range t stg ?65 to +150 c characteristics symbol value unit thermal resistance dip soic qfp ja ja ja 60 60 60 c/w c/w c/w tpg 75 05sr3.book page 1 thursday, august 4, 2005 1:08 pm
freescale 11-2 mc68hc05sr3 electrical specifications 11 11.3 dc electrical characteristics table 11-1 dc electrical characteristics for 5v operation (v dd =5.0vdc 10%, v ss =0vdc, temperature range=0 to 70 c) characteristics symbol minimum typical maximum unit output voltage i load = ?10 a i load = +10 a v oh v ol v dd ?0.1 ? ? ? ? 0.1 v v output high voltage (i load =?0.8ma) all ports v oh v dd ?0.8 ? ? v output low voltage (i load =+1.6ma) all ports v ol ?0.10.4v output high current (v ol =2.5v) all ports (v ol =3.0v) pb5-pb7 in low-current mode i oh i oh 10 2 ? ? ? ? ma ma output low current (v ol =2.5v) all ports (v ol =3.0v) pb5-pb7 in low-current mode i ol i ol 10 2 ? ? ? ? ma ma total i/o port current either source or sink i port ?100?ma input high voltage pa0-pa7, pb0, pb1, irq , reset , osc1 v ih 0.7 v dd ?v dd v input low voltage pa0-pa7, pb0, pb1, irq , reset , osc1 v il v ss ?0.2 v dd v supply current: run wait stop 25 c 0 c to +70 c (standard) ?40 c to +85 c (extended) i dd ? ? ? ? ? 5.0 1.3 ? ? ? 7.0 2.5 20 30 40 ma ma a a a i/o ports high-z leakage current pa0-pa7, pb0-pb7, pc0-pc7, pd0-pd7 i il ?? 10 a input current reset , irq , osc1 i in ?? 1 a capacitance ports (as input or output) reset , irq , osc1, osc2 c out c in ? ? ? ? 12 8 pf pf low voltage reset threshold v lvr 2.8 3.5 4.2 v pull-up resistor pa0-pa7, pb0-pb7, pc0-pc7, pd0-pd7 reset , irq r pu 14 85 36 100 50 176 k ? k ? notes: (1) all values shown reflect average measurements. (2) typical values at mi dpoint of voltage range, 25 c only. (3) wait i dd : only timer system active. (4) wait, stop i dd : all ports configured as inputs, v il =0.2vdc, v ih =v dd ?0.2vdc. (5) run (operating) i dd , wait i dd : measured using external square wave clock source to osc1 (f osc =2.0mhz), all inputs 0.2vdc from rail; no dc loads, less than 50pf on all outputs, c l =20pf on osc2. (6) stop i dd measured with osc1=v ss . (7) wait i dd is affected linearly by the osc2 capacitance. tpg 76 05sr3.book page 2 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale 11-3 electrical specifications 11 table 11-2 dc electrical characteristics for 3v operation (v dd =3.0vdc 10%, v ss =0vdc, temperature range=0 to 70 c) characteristics symbol minimum typical maximum unit output voltage i load = ?10 a i load = +10 a v oh v ol v dd ?0.1 ? ? ? ? 0.1 v v output high voltage (i load =?0.8ma) all ports v oh v dd ?0.3 ? ? v output low voltage (i load =+1.6ma) all ports v ol ?0.10.3v output high current (v oh =1.0v) all ports i oh 2.7 3.5 4.7 ma output low current (v ol =2.0v) all ports i ol 3.0 4.0 5.2 ma total i/o port current either source or sink i port ? 100 ? ma input high voltage pa0-pa7, pb0, pb1, irq , reset , osc1 v ih 0.7 v dd ?v dd v input low voltage pa0-pa7, pb0, pb1, irq , reset , osc1 v il v ss ?0.2 v dd v supply current: run wait stop 25 c 0 c to +70 c (standard) ?40 c to +85 c (extended) i dd ? ? ? ? ? 2.4 0.75 ? ? ? 3.5 1.5 20 30 40 ma ma a a a i/o ports high-z leakage current pa0-pa7, pb0-pb7, pc0-pc7, pd0-pd7 i il ?? 10 a input current reset , irq , osc1 i in ?? 1 a capacitance ports (as input or output) reset , irq , osc1, osc2 c out c in ? ? ? ? 12 8 pf pf pull-up resistor pa0-pa7, pb0-pb7, pc0-pc7, pd0-pd7 reset , irq r pu 14 85 36 100 50 176 k ? k ? notes: (1) all values shown reflec t average measurements. (2) typical values at midpoint of voltage range, 25 c only. (3) wait i dd : only timer system active. (4) wait, stop i dd : all ports configured as inputs, v il =0.2vdc, v ih =v dd ?0.2vdc. (5) run (operating) i dd , wait i dd : measured using external square wave clock source to osc1 (f osc =2.0mhz), all inputs 0.2vdc from rail; no dc loads, less than 50pf on all outputs, c l =20pf on osc2. (6) stop i dd measured with osc1=v ss . (7) wait i dd is affected linearly by the osc2 capacitance. tpg 77 05sr3.book page 3 thursday, august 4, 2005 1:08 pm
freescale 11-4 mc68hc05sr3 electrical specifications 11 11.4 adc electrica l characteristics table 11-3 adc electrical characteristics for 5v and 3v operation characteristics parameter minimum maximum unit resolution number of bits resolved by the adc 8 8 bits absolute accuracy difference between the actual input voltage and the full-scale equivalent of the binary code output code for all errors. (1) ? ? 1.5 (v dd =5v) 2 (v dd =3.3v) lsb lsb conversion range analog input voltage range v rl v rh v power-up time adc power-up time delay, t adon ? 500 s v rh maximum analog reference voltage v rl v dd +0.1 v v rl minimum analog reference voltage v ss ?0.1 v rh v conversion time total time to perform a single analog to digital conversion (a) external clock (osc1, osc2) (b) internal rc oscillator ? ? 32 32 t cyc t cyc monotonicity conversion result never decreases with an increase in input voltage and has no missing codes inherent (within total error) zero-input reading conversion result when v in =v rl 00 ? hex full-scale reading conversion result when v in =v rh ? ff hex sample acquisition time analog input acquisition sampling (2) (a) external clock (osc1, osc2) (b) internal rc oscillator ? ? 12 12 t cyc s input capacitance input capacitance on an0-an3 ? 8 pf input leakage input leakage on adc pins (3) an0, an1, an2, an3, v rl , v rh ? 400 na notes: (1) error includes quantization. adc accu racy may decrease proportionately as v dd is reduced below 3.0v. (2) source impedances greater than 10k ? adversely affect internal rc c harging time during input sampling. (3) the external system error caused by i nput leakage current is approxim ately equal to the product of r source and input curren t. tpg 78 05sr3.book page 4 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale 11-5 electrical specifications 11 11.5 control timing table 11-4 control timing for 5v operation (v dd =5.0vdc 10%, v ss =0vdc, temperature range=0 to 70 c) characteristics symbol minimum maximum unit frequency of operation rc oscillator option crystal option external clock option f osc 0.1 0.1 dc 4.0 4.0 4.0 mhz mhz mhz internal operating frequency (f osc /2) rc oscillator crystal external clock f op ? ? dc 2.0 2.0 2.0 mhz mhz mhz processor cycle time (1/f op )t cyc 500 ? ns rc oscillator stabilization time t rcon ?1ms crystal oscillator start-up time (crystal oscillator) t oxov ?100ms stop recovery start-up time (crystal oscillator) t ilch ?100ms reset pulse width low t rl 1.5 ? t cyc timer resolution (2) t resl see note (2) ? t cyc interrupt pulse width low (edge-triggered) t ilih 125 ? ns interrupt pulse period t ilil see note (3) ? t cyc pa0-pa7 interrupt pulse wi dth high (edge-triggered) t ihil 125 ? ns pa0-pa7 interrupt pulse period t ihih see note (3) ? t cyc osc1 pulse width t 90 ? ns rc oscillator frequency combined stability (4) f osc =2.0mhz, v dd =5.0vdc 10%, t a =-40 c to +85 c f osc =2.0mhz, v dd =5.0vdc 10%, t a =0 c to +40 c ? f osc ? f osc ? ? 25 15 % % notes: (1) v dd =5.0vdc 10%, v ss =0vdc, t a =t l to t h (2) the timer input pin is the limiting factor in determining timer resolution. (3) the minimum period t ilil or t ihih should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 t cyc . (4) effects of processing, temperature, and supply vo ltage (excluding tolerances of external r and c). tpg 79 05sr3.book page 5 thursday, august 4, 2005 1:08 pm
freescale 11-6 mc68hc05sr3 electrical specifications 11 table 11-5 control timing for 3v operation (v dd =3.0vdc 10%, v ss =0vdc, temperature range=0 to 70 c) characteristics symbol minimum maximum unit frequency of operation rc oscillator option crystal option external clock option f osc 0.1 0.1 dc 2.0 2.0 2.0 mhz mhz mhz internal operating frequency (f osc /2) rc oscillator crystal external clock f op ? ? dc 1.0 1.0 1.0 mhz mhz mhz processor cycle time (1/f op )t cyc 1000 ? ns rc oscillator stabilization time t rcon ?2ms crystal oscillator start-up time (crystal oscillator) t oxov ? 200 ms stop recovery start-up time (crystal oscillator) t ilch ? 200 ms reset pulse width low t rl 1.5 ? t cyc timer resolution (2) t resl see note (2) ? t cyc interrupt pulse width low (edge-triggered) t ilih 250 ? ns interrupt pulse period t ilil see note (3) ? t cyc pa0-pa7 interrupt pulse wi dth high (edge-triggered) t ihil 250 ? ns pa0-pa7 interrupt pulse period t ihih see note (3) ? t cyc osc1 pulse width t 180 ? ns rc oscillator frequency combined stability (4) f osc =2.0mhz, v dd =3.0vdc 10%, t a =?40 c to +85 c f osc =2.0mhz, v dd =3.0vdc 10%, t a =0 c to +40 c ? f osc ? f osc ? ? 35 20 % % notes: (1) v dd =3.0vdc 10%, v ss =0vdc, t a =t l to t h (2) the timer input pin is the limiting fa ctor in determining timer resolution. (3) the minimum period t ilil or t ihih should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 t cyc . (4) effects of processing, temperature, and supply vo ltage (excluding tolerances of external r and c). tpg 80 05sr3.book page 6 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 motorola 12-1 mechanical specifications 12 12 mechanical specifications this section provides the mechanical dimensions for the 40-pin dip, 42-pin sdip and 44-pin qfp packages for the mc68hc05sr3. tpg 81 05sr3.book page 1 thursday, august 4, 2005 1:08 pm
motorola 12-2 mc68hc05sr3 mechanical specifications 12 12.1 40-pin dip package (case 711-03) 12.2 42-pin sdip package (case 858-01) figure 12-1 40-pin dip package figure 12-2 42-pin sdip package

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mc68hc05sr3 motorola 12-3 mechanical specifications 12 12.3 44-pin qfp package (case 824a-01) figure 12-3 44-pin qfp package

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motorola 12-4 mc68hc05sr3 mechanical specifications 12 this page left bl ank intentionally tpg 84 05sr3.book page 4 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale a-1 mc68hc705sr3 a a mc68hc705sr3 this appendix summarizes the differences between the mc68hc05sr3 and mc68hc705sr3. the same information can also be found in appropriate sections of the book. the mc68hc705sr3 is an eprom version of the mc68hc05sr3. the 3840 bytes of user rom in the mc68hc05sr3 are replaced by 3840 bytes of user eprom. a.1 features functionally equivalent to mc68hc05sr3 3840 bytes of user eprom eprom bootstrap mode replaces self-check mode on the mc68hc05sr3 available in the following packages: otp 40-pin pdip, windowed eprom 40-pin ceramic dip, otp 42-pin sdip, and 44-pin qfp tpg 85 05sr3.book page 1 thursday, august 4, 2005 1:08 pm
freescale a-2 mc68hc05sr3 mc68hc705sr3 a a.2 modes of operation the mc68hc705sr3 has two modes of operation ? user mode and eprom bootstrap mode. table a-1 shows the condition s required to enter each mo de on the rising edge of reset . a.3 user mode the normal operating mode of the mc68hc705sr3 is the user mode. user mode will be entered on the rising edge of reset when the v pp and pb1 pins are between v ss and v dd . warning: in the mc68hc705sr3, all vectors are fetc hed from eprom in user mode; therefore, the eprom must be programmed (via the bootstrap mode) before the device is powered up in user mode. a.4 bootstrap mode the bootstrap mode is provided as a mean of self-programming mc68hc705sr3 eprom with minimal circuitry, and can only run in the cryst al oscillator mode. bootstrap mode will be entered on the rising edge of reset when the v pp pin is at v tst (2 v dd ) and pb1 pin is at v dd . once in the bootstrap mode, pb1 can then be used for other purposes. after entering the bootstrap mode, cpu branches to the bootstrap program and carries out the eprom programming routine. the user eprom consists of 3840 bytes, from location $1000 to $1eff. this program handles copying of user code from an external eprom into the on-chip eprom. the bootstrap function does not have to be done from an external eprom, but it may be done from a host. the user code must be a one-to-one correspondence with the internal eprom addresses. table a-1 mc68hc705sr3 operating mode entry conditions reset v pp pb1 mode v ss to v dd v ss to v dd user v tst v dd bootstrap v tst =2 v dd 5v tpg 86 05sr3.book page 2 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale a-3 mc68hc705sr3 a a.4.1 eprom programming programming boards are available from freescale for programming the on-chip eprom. please contact your freescale representative. the programming control register (pcr) is pr ovided for eprom programming. the function of the eprom depends on the device operating mode. a.4.2 program contro l register (pcr) elat - eprom latch control 1 (set) ? eprom address and data bus configured for programming (writes to eprom cause address data to be latched). eprom is in programming mode and cannot be read if elata is 1. this bit should not be set unless a programming voltage is applied to the v pp pin. 0 (clear) ? eprom address and data bus configured for normal reads. pgm - eprom program command 1 (set) ? programming power connected to the eprom array. if elat 1 then pgm = 0. 0 (clear) ? programming power disconnected from the eprom array. a.4.3 eprom programming sequence programming the eprom of the mc68hc705sr3 is as follows: 1) set the elat bit. 2) write the data to be programmed to the address to be programmed. 3) set the pgm bit. 4) delay for 1ms. 5) clear the pgm and the elat bits. the last action may be carried out in a single cpu wr ite operation. it is important to remember that an external programming voltage must be applied to the v pp pin while programming, but should be equal to v dd during normal operation. example shows address $1900 is programmed with $00. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset $0d reserved elat pgm ---- --00 tpg 87 05sr3.book page 3 thursday, august 4, 2005 1:08 pm
freescale a-4 mc68hc05sr3 mc68hc705sr3 a clr pcr ;reset pcr ldx #$00 ;load index register with 00 bset 1,pcr ;set elat bit lda #$00 ;load data=00 in to a sta $1900,x ;latch data and address bset 0,pcr ;program jsr delay ;call delay subroutine for 1ms clr pcr ;reset pcr a.5 mask option register (mor) the mask option register (mor) contains prog rammable eprom bits to control mask options, and cannot be changed in user mode. the erased st ate are zeros. this register is latched upon reset going away. smd ? slow mode at power-on when programmed to ?1?, this bit enables slow mode at power-up. operating frequency, f op =f osc 2 16=f osc 32. sec ? eprom security when programmed to ?1?, this bit disables so me functions of the bo otstrap mode, preventing external reading of eprom content. tmr2:tmr0 ? power-on reset delay the amount power-on reset delay is set by programming these three bits. the delay is selected as follows: address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset mask option register (mor) $0fff smd sec tmr2 tmr1 tmr0 rc unaffected tmr2 tmr1 tmr0 delay (instruction cycles) 000 256 001 512 0 1 0 1024 0 1 1 2048 1 0 0 4096 1 0 1 8192 1 1 0 16384 1 1 1 32768 tpg 88 05sr3.book page 4 thursday, august 4, 2005 1:08 pm
mc68hc05sr3 freescale a-5 mc68hc705sr3 a rc ? rc or crystal oscillator option 1 (set) ? resistor option selected. 0 (clear) ? crystal option selected. a.6 pin assignments see section 2.3 for pin assignments for the available packages. tpg 89 05sr3.book page 5 thursday, august 4, 2005 1:08 pm
freescale a-6 mc68hc05sr3 mc68hc705sr3 a this page left bl ank intentionally tpg 90 05sr3.book page 6 thursday, august 4, 2005 1:08 pm
1 2 3 4 5 6 7 8 9 10 11 12 a general description pin descriptions input/output ports memory and registers resets and interrupts timer analog to digital converter cpu core and in struction set low power modes operating modes electrical specifications mechanical specifications mc68hc705sr3 tpg 91 05sr3.book page 7 thursday, august 4, 2005 1:08 pm
1 2 3 4 5 6 7 8 9 10 11 12 a general description pin descriptions input/output ports memory and registers resets and interrupts timer analog to digi tal converter cpu core and instruction set low power modes operating modes electrical specifications mechanical specifications mc68hc705sr3 tpg 92 05sr3.book page 8 thursday, august 4, 2005 1:08 pm

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